High Performance CMOS Level up Conversion for Systems with Low-Voltage Power Supply

Abstract

A single supply CMOS non-inverting level shifter circuit, con-Is, for converting input signals from 0.3V up to 0.7V is presented. The circuit is optimized and pre-layout simulated in a 65nm CMOS process technology. At the target design voltage of 0.3V, the level shifter has a propagation delay of 1.06ns, an energy consumption of only 0.790, and energy-delay product of 0.84pJns for capacitive load of 1pf. Simulation results arc compared to other similar published works at a frequency of 500 MHz, and it shown that the proposed circuit outperforms them.