System Level Methodology based on VIPPE applied to the implementation of a Scalable Video Decoder on the ZynQ platform

Abstract

One of the first problems that a hardware designer needs to solve when facing a new and complex electronic design, is to know in advance where the critical parts of the design are, and how many resources the design will require. This information will ease the developing of feasible systems and will help in the design of well suited architectures. The Open SVC (Scalable Video Coding) Decoder (OSD) is an open source system created at IETR/INSA at Rennes that implements a SV decoder written in language. The scalable video encoder supposes an important overload compared with its counterpart non-scalable video encoder, which inherently already exhibits a very high computational load. Due to the huge number of functions that form part of the SV video decoder, a set of internal modules that better describes the internal structure of the decoder has been defined. In this scenario, two aspects have been selected to be the critical ones: the computational load and the transaction of data. In order to adopt appropriate decisions related with the system implementation This paper presents a methodology based on VIPPE that will be used to perform the profiling of a complex system like the OSD over a user-defined platform, the ZynQ from Xilinx in this case, composed by two ARM cores and an FPGA. The profiling results will guided the implementation of the OSD on the aforementioned ZynQ platform. The methodology can be easily extrapolated to any other complex design.