Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/55096
Campo DC Valoridioma
dc.contributor.authorRodriguez, Alfonsoen_US
dc.contributor.authorSantos, Lucanaen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.contributor.authorTorre, Eduardo De Laen_US
dc.date.accessioned2019-02-18T16:30:01Z-
dc.date.available2019-02-18T16:30:01Z-
dc.date.issued2019en_US
dc.identifier.issn2169-3536en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/55096-
dc.description.abstractHyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-the-art hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget).en_US
dc.languageengen_US
dc.relation.ispartofIEEE Accessen_US
dc.sourceIEEE Access[ISSN 2169-3536],v. 7, p. 10644-10652, (2019)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherFpga Implementationen_US
dc.subject.otherData Compressionen_US
dc.subject.otherDynamic And Partial Reconfigurationen_US
dc.subject.otherFpgasen_US
dc.subject.otherHigh-Performance Embedded Computingen_US
dc.subject.otherHyperspectral Imagesen_US
dc.subject.otherOn-Board Processingen_US
dc.titleScalable hardware-based on-board processing for run-time adaptive lossless hyperspectral compressionen_US
dc.typeinfo:eu-repo/semantics/articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ACCESS.2019.2892308en_US
dc.identifier.scopus85061079827-
dc.identifier.isi000458011000001-
dc.contributor.authorscopusid56972626600-
dc.contributor.authorscopusid54391653200-
dc.contributor.authorscopusid35609452100-
dc.contributor.authorscopusid50162474400-
dc.description.lastpage10652en_US
dc.identifier.issue8610106-
dc.description.firstpage10644en_US
dc.relation.volume7en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid31468442-
dc.contributor.daisngid29585558-
dc.contributor.daisngid116294-
dc.contributor.daisngid626981-
dc.description.numberofpages9en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Rodriguez, A-
dc.contributor.wosstandardWOS:Santos, L-
dc.contributor.wosstandardWOS:Sarmiento, R-
dc.contributor.wosstandardWOS:De La Torre, E-
dc.identifier.ulpgces
dc.description.sjr0,775
dc.description.jcr3,745
dc.description.sjrqQ1
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSantos Falcón, Lucana-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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