Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/54963
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dc.contributor.authorOrtiz, Albertoen_US
dc.contributor.authorGuerra Hernández, Raúl Celestinoen_US
dc.contributor.authorLopez, Sebastianen_US
dc.contributor.authorOtero, Andrésen_US
dc.contributor.authorSarmiento Rodríguez, Robertoen_US
dc.contributor.authorde la Torre, Eduardoen_US
dc.contributor.authorRodríguez, Alfonsoen_US
dc.date.accessioned2019-02-18T15:55:08Z-
dc.date.available2019-02-18T15:55:08Z-
dc.date.issued2018en_US
dc.identifier.issn2072-4292en_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/54963-
dc.description.abstractSpace missions are facing disruptive innovation since the appearance of small, lightweight, and low-cost satellites (e.g., CubeSats). The use of commercial devices and their limitations in cost usually entail a decrease in available on-board computing power. To face this change, the on-board processing paradigm is advancing towards the clustering of satellites, and moving to distributed and collaborative schemes in order to maintain acceptable performance levels in complex applications such as hyperspectral image processing. In this scenario, hybrid hardware/software and reconfigurable computing have appeared as key enabling technologies, even though they increase complexity in both design and run time. In this paper, the ARTICo(3) framework, which abstracts and eases the design and run-time management of hardware-accelerated systems, has been used to deploy a networked implementation of the Fast UNmixing (FUN) algorithm, which performs linear unmixing of hyperspectral images in a small cluster of reconfigurable computing devices that emulates a distributed on-board processing scenario. Algorithmic modifications have been proposed to enable data-level parallelism and foster scalability in two ways: on the one hand, in the number of accelerators per reconfigurable device; on the other hand, in the number of network nodes. Experimental results motivate the use of ARTICo(3)-enabled systems for on-board processing in applications traditionally addressed by high-performance on-Earth computation. Results also show that the proposed implementation may be better, for certain configurations, than an equivalent software-based solution in both performance and energy efficiency, achieving great scalability that is only limited by communication bandwidth.en_US
dc.languageengen_US
dc.relationPlataforma Hw/Sw Distribuida Para El Procesamiento Inteligente de Información Sensorial Heterogenea en Aplicaciones de Supervisión de Grandes Espacios Naturalesen_US
dc.relationTEC2017-86722-C4-2-R PLATAFORMA HW/SW DISTRIBUIDA PARA EL PROCESAMIENTO INTELIGENTE DE INFORMACION SENSORIAL HETEROGENEA EN APLICACIONES DE SUPERVISION DE GRANDES ESPACIOS NATURALESen_US
dc.relation.ispartofRemote Sensingen_US
dc.sourceRemote Sensing [ISSN 2072-4292], v. 10(11), 1790en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherParallel Implementationen_US
dc.subject.otherFast Algorithmen_US
dc.subject.otherClassificationen_US
dc.subject.otherCapabilitiesen_US
dc.subject.otherCompressionen_US
dc.subject.otherSatellitesen_US
dc.subject.otherHybriden_US
dc.subject.otherChainen_US
dc.subject.otherHyperspectral Imagingen_US
dc.subject.otherLinear Unmixingen_US
dc.subject.otherFpgasen_US
dc.subject.otherOn-Board Processingen_US
dc.subject.otherArtico(3)en_US
dc.titleA runtime-scalable and hardware-accelerated approach to on-board linear unmixing of hyperspectral imagesen_US
dc.typeinfo:eu-repo/semantics/articleen_US
dc.typeArticleen_US
dc.identifier.doi10.3390/rs10111790en_US
dc.identifier.scopus85057127653-
dc.identifier.isi000451733800121-
dc.contributor.authorscopusid57204770113-
dc.contributor.authorscopusid56972626600-
dc.contributor.authorscopusid56333613300-
dc.contributor.authorscopusid57187722000-
dc.contributor.authorscopusid35868116400-
dc.contributor.authorscopusid35609452100-
dc.contributor.authorscopusid6603668216-
dc.identifier.issue1790-
dc.relation.volume10en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.contributor.daisngid29777603-
dc.contributor.daisngid31468442-
dc.contributor.daisngid2216671-
dc.contributor.daisngid465777-
dc.contributor.daisngid298843-
dc.contributor.daisngid116294-
dc.contributor.daisngid626981-
dc.description.numberofpages21en_US
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Ortiz, A-
dc.contributor.wosstandardWOS:Rodriguez, Alfonso-
dc.contributor.wosstandardWOS:Guerra, R-
dc.contributor.wosstandardWOS:Lopez, S-
dc.contributor.wosstandardWOS:Otero, A-
dc.contributor.wosstandardWOS:Sarmiento, R-
dc.contributor.wosstandardWOS:de la Torre, E-
dc.identifier.ulpgcen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.sjr1,43
dc.description.jcr4,118
dc.description.sjrqQ1
dc.description.jcrqQ1
dc.description.scieSCIE
item.grantfulltextopen-
item.fulltextCon texto completo-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-4303-3051-
crisitem.author.orcid0000-0002-2360-6721-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameGuerra Hernández,Raúl Celestino-
crisitem.author.fullNameLópez Suárez, Sebastián Miguel-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
crisitem.project.principalinvestigatorLópez Suárez, Sebastián Miguel-
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