Optimization of the delta-doped layer in P-HFETs at medium/high temperatures

Abstract

The use of delta-doping in HFET processes has made the development of transistor circuits and logic gates possible, for very high-frequency/speed or low-power applications. This behaviour of the PHFET device is due to fast quantum well conduction. However, the effect of the operating temperature range is critical. This range depends on the transistor and circuit activity, the packaging technique, and the external operating conditions. Temperature strongly affects the device ability to confine the current flow into the quantum well channel. In this paper the effect of temperature and delta-doping concentration on the performance of the device is investigated by means of simulated experiments. The results are analytically and qualitatively discussed, showing how to fine tune the delta-doping concentration in order to optimize the P-HFET behaviour from medium- to high-temperature conditions, [300, 500] K.