Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/52230
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Celinski, P. | |
dc.contributor.author | López, J. F. | |
dc.contributor.author | Al-Sarawi, S. | |
dc.contributor.author | Abbott, D. | |
dc.date.accessioned | 2018-11-25T18:32:07Z | - |
dc.date.available | 2018-11-25T18:32:07Z | - |
dc.date.issued | 2000 | |
dc.identifier.issn | 0013-5194 | |
dc.identifier.uri | http://hdl.handle.net/10553/52230 | - |
dc.description.abstract | A neu-MOS like transistor structure using complementary GaAs HIGFET transistors, neu-GaAs, which uses capacitively coupled inputs onto a floating gate is presented. The design and simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for a very significant reduction in transistor count and area for equal power dissipation, through the use of neu-GaAs in VLSI design. A neu-GaAs design is presented which does not require floating gate initialization due to the presence of a small gate leakage current in the HIGFET structure. | |
dc.publisher | 0013-5194 | |
dc.relation.ispartof | Electronics letters | |
dc.source | Electronics Letters[ISSN 0013-5194],v. 36, p. 424-425 | |
dc.title | Complementary neu-GaAs structure | |
dc.type | info:eu-repo/semantics/Article | es |
dc.type | Article | es |
dc.identifier.doi | 10.1049/el:20000384 | |
dc.identifier.scopus | 17544392807 | |
dc.contributor.authorscopusid | 6701421283 | |
dc.contributor.authorscopusid | 7404444793 | |
dc.contributor.authorscopusid | 7004170747 | |
dc.contributor.authorscopusid | 56053895400 | |
dc.description.lastpage | 425 | |
dc.description.firstpage | 424 | |
dc.relation.volume | 36 | |
dc.type2 | Artículo | es |
dc.date.coverdate | Marzo 2000 | |
dc.identifier.ulpgc | Sí | es |
dc.description.jcr | 0,931 | |
dc.description.jcrq | Q2 | |
dc.description.scie | SCIE | |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-6304-2801 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | López Feliciano, José Francisco | - |
Colección: | Artículos |
Citas SCOPUSTM
2
actualizado el 17-nov-2024
Citas de WEB OF SCIENCETM
Citations
2
actualizado el 17-nov-2024
Visitas
85
actualizado el 21-sep-2024
Google ScholarTM
Verifica
Altmetric
Comparte
Exporta metadatos
Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.