Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/52224
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Celinski, P. | |
dc.contributor.author | López, J. F. | |
dc.contributor.author | Al-Sarawi, S. | |
dc.contributor.author | Abbott, D. | |
dc.date.accessioned | 2018-11-25T18:29:15Z | - |
dc.date.available | 2018-11-25T18:29:15Z | - |
dc.date.issued | 2002 | |
dc.identifier.issn | 0013-5194 | |
dc.identifier.uri | http://hdl.handle.net/10553/52224 | - |
dc.publisher | 0013-5194 | |
dc.relation.ispartof | Electronics letters | |
dc.source | Electronics Letters[ISSN 0013-5194],v. 38, p. 633-635 | |
dc.title | Compact parallel (m,n) counters based on self-timed threshold logic | |
dc.type | info:eu-repo/semantics/article | es |
dc.type | Article | es |
dc.identifier.doi | 10.1049/el:20020438 | |
dc.identifier.scopus | 0037142559 | |
dc.contributor.authorscopusid | 6701421283 | |
dc.contributor.authorscopusid | 7404444793 | |
dc.contributor.authorscopusid | 7004170747 | |
dc.contributor.authorscopusid | 56053895400 | |
dc.description.lastpage | 635 | |
dc.description.firstpage | 633 | |
dc.relation.volume | 38 | |
dc.type2 | Artículo | es |
dc.identifier.ulpgc | Sí | es |
dc.description.sjr | 1,542 | |
dc.description.sjrq | Q1 | |
dc.description.scie | SCIE | |
item.fulltext | Sin texto completo | - |
item.grantfulltext | none | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-6304-2801 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | López Feliciano, José Francisco | - |
Appears in Collections: | Artículos |
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