Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50506
Title: Tolerating branch predictor latency on SMT
Authors: Falcón, Ayose
Santana, Oliverio J. 
Ramírez, Alex
Valero, Mateo
UNESCO Clasification: 330406 Arquitectura de ordenadores
Keywords: Branch predictor delay
Decoupled fetch
Predictor pipelining
SMT
Issue Date: 2003
Journal: Lecture Notes in Computer Science 
Abstract: Simultaneous Multithreading (SMT) tolerates latency by executing instructions from multiple threads. If a thread is stalled, resources can be used by other threads. However, fetch stall conditions caused by multi-cycle branch predictors prevent SMT to achieve all its potential performance, since the flow of fetched instructions is halted. This paper proposes and evaluates solutions to deal with the branch predictor delay on SMT. Our contribution is two-fold: we describe a decoupled implementation of the SMT fetch unit, and we propose an inter-thread pipelined branch predictor implementation. These techniques pro-ve to be effective for tolerating the branch predictor access latency.
URI: http://hdl.handle.net/10553/50506
ISBN: 978-3-540-20359-9
ISSN: 0302-9743
DOI: 10.1007/978-3-540-39707-6_7
Source: Veidenbaum A., Joe K., Amano H., Aiso H. (eds) High Performance Computing. ISHPC 2003. Lecture Notes in Computer Science, vol 2858. Springer, Berlin, Heidelberg
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