Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50505
Title: A low-complexity fetch architecture for high-performance superscalar processors
Authors: Santana, Oliverio J. 
Ramirez, Alex
Larriba-Pey, Josep L.
Valero, Mateo
UNESCO Clasification: 330406 Arquitectura de ordenadores
Keywords: Branch prediction
Design
Fetch architecture
High performance
Instruction stream, et al
Issue Date: 2004
Journal: Transactions on Architecture and Code Optimization 
Abstract: Fetch engine performance is a key topic in superscalar processors, since it limits the instruction-level parallelism that can be exploited by the execution core. In the search of high performance, the fetch engine has evolved toward more efficient designs, but its complexity has also increased.In this paper, we present the stream fetch engine, a novel architecture based on the execution of long streams of sequential instructions, taking maximum advantage of code layout optimizations. We describe our design in detail, showing that it achieves high fetch performance, while requiring less complexity than other state-of-the-art fetch architectures.
URI: http://hdl.handle.net/10553/50505
ISSN: 1544-3566
DOI: 10.1145/1011528.1011532
Source: ACM Transactions on Architecture and Code Optimization [ISSN 1544-3566], v. 1 (2), p. 220-245
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