Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/50496
DC FieldValueLanguage
dc.contributor.authorVera, Javieren_US
dc.contributor.authorCazorla, Francisco J.en_US
dc.contributor.authorPajuelo, Alexen_US
dc.contributor.authorSantana, Oliverio J.en_US
dc.contributor.authorFernández, Enriqueen_US
dc.contributor.authorValer, Mateoen_US
dc.date.accessioned2018-11-24T16:29:28Z-
dc.date.available2018-11-24T16:29:28Z-
dc.date.issued2007en_US
dc.identifier.isbn0-7695-2944-5en_US
dc.identifier.issn1089-795Xen_US
dc.identifier.urihttp://hdl.handle.net/10553/50496-
dc.description.abstractNowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements of a given workload execution are taken. A metric combines those measurements to obtain a final evaluation result. However, since current evaluation methodologies do not provide representative measurements for these metrics, the analysis and evaluation of novel ideas could be either unfair or misleading. Given the potential impact of multithreaded architectures on current andfuture processor designs, it is crucial to develop an accurate evaluation methodology for them. This paper presents FAME, a new evaluation methodology aimed to fairly measure the performance of rnultithreaded processors. FAME reexecutes all traces in a rnultithreaded workload until all of them are fairly represented in the final measurements taken from the workload. We compare FAME with previously used methodologies for both architectural research simulators and real processors. Our results show that FAME provides more accurate measurements than other methodologies, becoming an ideal evaluation methodology to analyze proposals for multithreaded architectures. © 2007 IEEE.-
dc.languageengen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.ispartofParallel Architectures and Compilation Techniques - Conference Proceedings, PACTen_US
dc.sourceParallel Architectures and Compilation Techniques - Conference Proceedings, PACT [ISSN 1089-795X], n. 4336221, p. 305-316en_US
dc.subject120326 Simulaciónen_US
dc.titleFAME: FAirly MEasuring multithreaded architecturesen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007en_US
dc.identifier.doi10.1109/PACT.2007.4336221en_US
dc.identifier.scopus47249121916-
dc.contributor.authorscopusid24476591600-
dc.contributor.authorscopusid55129883300-
dc.contributor.authorscopusid9733817100-
dc.contributor.authorscopusid7003605046-
dc.contributor.authorscopusid36476145100-
dc.contributor.authorscopusid24476861800-
dc.description.lastpage316en_US
dc.identifier.issue4336221-
dc.description.firstpage305en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.date.coverdateDiciembre 2007en_US
dc.identifier.conferenceidevents121346-
dc.identifier.ulpgces
dc.description.ggs2
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR SIANI: Inteligencia Artificial, Robótica y Oceanografía Computacional-
crisitem.author.deptIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.deptDepartamento de Informática y Sistemas-
crisitem.author.orcid0000-0001-7511-5783-
crisitem.author.parentorgIU Sistemas Inteligentes y Aplicaciones Numéricas-
crisitem.author.fullNameSantana Jaria, Oliverio Jesús-
crisitem.author.fullNameFernández García, Enrique-
crisitem.event.eventsstartdate15-09-2007-
crisitem.event.eventsenddate19-09-2007-
Appears in Collections:Actas de congresos
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