1. accedaCRIS
  2. Publicaciones
  3. Actas de congresos
Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49698
DC FieldValueLanguage
dc.contributor.authorNooshabadi, S.en_US
dc.contributor.authorMontiel-Nelson, J. A.en_US
dc.contributor.authorVisweswaran, G. S.en_US
dc.contributor.authorNagchoudhurhi, D.en_US
dc.contributor.otherMontiel-Nelson, Juan-
dc.date.accessioned2018-11-24T09:59:04Z-
dc.date.available2018-11-24T09:59:04Z-
dc.date.issued1997en_US
dc.identifier.isbn0-8186-7755-4en_US
dc.identifier.urihttp://hdl.handle.net/10553/49698-
dc.description.abstractIn this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropipelined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.en_US
dc.languageengen_US
dc.relation.ispartofProceedings of the IEEE International Conference on VLSI Designen_US
dc.sourceProceedings of the IEEE International Conference on VLSI Design, p. 451-456en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherFinite impulse response filteren_US
dc.subject.otherClocksen_US
dc.subject.otherVery large scale integrationen_US
dc.subject.otherCMOS technologyen_US
dc.subject.otherDelayen_US
dc.subject.otherCMOS logic circuitsen_US
dc.subject.otherComputer architectureen_US
dc.titleMicropipeline architecture for multiplier-less FIR filtersen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.identifier.scopus0030819335-
dc.identifier.isiA1997BH04E00079-
dcterms.isPartOfTenth International Conference On Vlsi Design, Proceedings-
dcterms.sourceTenth International Conference On Vlsi Design, Proceedings, p. 451-456-
dc.contributor.authorscopusid6602486254-
dc.contributor.authorscopusid6603626866-
dc.contributor.authorscopusid6602989195-
dc.contributor.authorscopusid6506131700-
dc.description.lastpage456en_US
dc.description.firstpage451en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:A1997BH04E00079-
dc.contributor.daisngid184255-
dc.contributor.daisngid480589-
dc.contributor.daisngid1238103-
dc.contributor.daisngid11371494-
dc.identifier.investigatorRIDK-6805-2013-
dc.utils.revisionSíen_US
dc.identifier.ulpgcSíes
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Instrumentación avanzada-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-4323-8097-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameMontiel Nelson, Juan Antonio-
Appears in Collections:Actas de congresos
Show simple item record

SCOPUSTM   
Citations

5
checked on Nov 24, 2024

Page view(s)

31
checked on Feb 4, 2023

Google ScholarTM

Check

Altmetric


Share


Export metadata


Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.