Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/49695
| Título: | Novel latch design for high-speed GaAs circuits | Autores/as: | Eshragian, K. Nooshabadi, S. Montiel-Nelson, J. A. |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Gallium arsenide Power consumption Latches |
Fecha de publicación: | 1997 | Publicación seriada: | Proceedings of the Australian Microelectronics Conference | Resumen: | A GaAs latch design suitable for dynamic logic families is presented. This novel concept is compared with other common GaAs logic circuits in terms of device count, area, clock rate and power consumption. The results demonstrate that the Single Phase Latch (SPL) achieves a throughput 5.7 greater than other dynamic latches while driving twice the capacitive load. It is the simplest, the fastest and consumes less power than other reported dynamic latch structures | URI: | http://hdl.handle.net/10553/49695 | Fuente: | Proceedings of the Australian Microelectronics Conference, p. 51-54 |
| Colección: | Actas de congresos |
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