|Title:||Novel latch design for high-speed GaAs circuits||Authors:||Eshragian, K.
Montiel-Nelson, J. A.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Gallium arsenide
|Issue Date:||1997||Journal:||Proceedings of the Australian Microelectronics Conference||Abstract:||A GaAs latch design suitable for dynamic logic families is presented. This novel concept is compared with other common GaAs logic circuits in terms of device count, area, clock rate and power consumption. The results demonstrate that the Single Phase Latch (SPL) achieves a throughput 5.7 greater than other dynamic latches while driving twice the capacitive load. It is the simplest, the fastest and consumes less power than other reported dynamic latch structures||URI:||http://hdl.handle.net/10553/49695||Source:||Proceedings of the Australian Microelectronics Conference, p. 51-54|
|Appears in Collections:||Actas de congresos|
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