|Title:||Efficient computation of the areapower consumption versus delay tradeoff curve for circuit critical path optimization||Authors:||Sosa González, Carlos Javier
Montiel-Nelson, J. A.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Energy consumption
Microelectronics, et al
|Issue Date:||2001||Journal:||ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings||Conference:||2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001||Abstract:||The paper introduces a novel methodology to obtain the entire areapower consumption versus delay tradeoff curve for the critical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the tradeoff curve, in this work only a subset of the Boolean network representing the circuit is optimized each time. Performance comparison and results based on the MCNC'91 set of two-level benchmark circuits are given. It is demonstrated that the proposed methodology produces tradeoff curves for large circuits of thousands of gates greatly reducing the computation complexity (measured in number of variables of an equivalent linear programming problem) by a factor up to 16 times.||URI:||http://hdl.handle.net/10553/49691||ISBN:||0780366859||Source:||ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings,v. 5 (922101), p. 527-530|
|Appears in Collections:||Actas de congresos|
checked on Dec 3, 2023
checked on Aug 13, 2022
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.