Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/49684
Título: Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder
Autores/as: Gupta, Amit Kumar
Nooshabadi, Saeid
Montiel-Nelson, Juan 
Clasificación UNESCO: 3307 Tecnología electrónica
Palabras clave: Very large scale integration
Computer programming
Field programmable gate arrays
Clocks
JPEG2000, et al.
Fecha de publicación: 2005
Publicación seriada: Proceedings of SPIE - The International Society for Optical Engineering 
Conferencia: VLSI Circuits and Systems II 
Resumen: In this paper we present the VLSI architecture for the buffer for tier-I of EBCOT encoder of JPEG2000. The buffer allows the integration of bit-plane coder and arithmetic coder module employing concurrent symbol processing technique. The buffer architecture is optimized by exploiting the natural image statistics to optimally choose the buffer length parameter. The overall architecture is implemented using Altera FPGA and experimental results show a savings of 59% in the hardware cost with minimal reduction in the overall throughput.
URI: http://hdl.handle.net/10553/49684
ISBN: 0-8194-5832-5
ISSN: 0277-786X
DOI: 10.1117/12.608585
Fuente: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5837 PART I (23), p. 185-192
Colección:Actas de congresos
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