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| Title: | Low power arithmetic circuits in feedthrough dynamic CMOS logic | Authors: | Navarro-Botello, Victor Montiel-Nelson, Juan A. Nooshabadi, Saeid Dyer, Mike |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | CMOS logic circuits CMOS technology Logic design Energy consumption Delay effects, et al |
Issue Date: | 2006 | Journal: | Midwest Symposium on Circuits and Systems | Conference: | 49th IEEE International Midwest Symposium on Circuits and Systems | Abstract: | This paper presents the design of low power high performance arithmetic circuits using the feedthrough logic (FTL) [1] concept. Low power FTL arithmetic circuits provide for smaller propagation time delay (2.6 times), lower energy consumption (31%), and similar combined delay, power consumption, and active area product, when compared with the standard CMOS technologies. | URI: | https://accedacris.ulpgc.es/handle/10553/49676 | ISBN: | 1424401739 | ISSN: | 1548-3746 | DOI: | 10.1109/MWSCAS.2006.382161 | Source: | Midwest Symposium on Circuits and Systems[ISSN 1548-3746],v. 1 (4267238), p. 709-712 |
| Appears in Collections: | Actas de congresos |
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