High performance CMOS 2-input NAND based on low-race split-level charge-recycling pass-transistor logic

Título:	High performance CMOS 2-input NAND based on low-race split-level charge-recycling pass-transistor logic
Autores/as:	García, José C. Montiel-Nelson, Juan A. Nooshabadi, Saeid
Clasificación UNESCO:	3307 Tecnología electrónica
Palabras clave:	Low-voltage low-energy high capacitive load charge-recycling
Fecha de publicación:	2009
Publicación seriada:	12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
Conferencia:	12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Resumen:	This paper presents the design of a highly efficient CMOS 2-input NAND (gcr-nand). When implemented on a 65nm CMOS technology, under 1pF capacitive loading condition, gcr-nand has a lower active area (3.4 times lower), and energy-delay product (56%) than the reference 2-input NAND (Iscpl-nand). Furthermore, gcr-nand is able to operate under a high output load.
URI:	http://hdl.handle.net/10553/49654
ISBN:	9780769537825
DOI:	10.1109/DSD.2009.181
Fuente:	12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 (5350167), p. 593-596
Colección:	Actas de congresos

Vista completa