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Title: | High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process | Authors: | García, José C. Montiel-Nelson, Juan A. Nooshabadi, Saeid |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | CMOS technology CMOS process Capacitors Delay Dynamic voltage scaling, et al |
Issue Date: | 2009 | Journal: | 2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 | Conference: | 2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 | Abstract: | This paper presents the design of a highly efficient CMOS level shifter qc-level shifter. Unlike many recent level shifters, the proposed qc-level shifter does not use bootstrap capacitors to minimize active area. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (2pF), qc-level shifter has a lower active area (94%), and energy-delay product (21.4%) than the reference bootstrap level shifter circuit (ts-level shifter). In comparison to a conventional shifter (c-level shifter)the corresponding reductions are 9.5% and 55%, respectively. Also qc-level shifter has very small effective input capacitance in comparison with ts-level shifter as it does not need a bootstrap capacitor connected to its input. | URI: | http://hdl.handle.net/10553/49653 | ISBN: | 9781424445219 | DOI: | 10.1109/ISCIT.2009.5340988 | Source: | 2009 9th International Symposium on Communications and Information Technology, ISCIT 2009 (5340988), p. 963-966 |
Appears in Collections: | Actas de congresos |
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