|Title:||Feedthrough: An energy efficient CMOS logic familyfor arithmetic circuits||Authors:||Navarro-Botello, Victor
Montiel-Nelson, Juan A.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||CMOS arithmetic circuits
CMOS digital integrated circuits
Low power design
High speed integrated circuits
|Issue Date:||2011||Journal:||CMOS Technology||Abstract:||In this chapter we present a comprehensive and up-to-date study on the feedthrough logic (FTL) concept for designing high performance arithmetic circuits in CMOS technology. The FTL logic family, for high speed and low power CMOS applications, was introduced by the authors in the recent past. FTL works successfully on the domino concept with the added feature that gates commence evaluation even before their input signals are valid. This is accomplished by means of initial quasi transition of all the FTL cells to a high gain point. This fact results in very fast evaluation time in the computational blocks for the final evaluation when inputs arrive. Furthermore, the well known problems of domino logic, such as the need for output inverters and charge redistribution, are completely eliminated, thus reducing the chip area and delay, and improving the performance. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, from the chip measurements, demonstrated superior performance of the FTL ripple carry adders (RCA) when compared with the dynamic domino and traditional CMOS logic styles. Our 14-bit low power implementation performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (3.11 times or 67.9%), when compared with the dynamic domino style. On the other hand, an 18-bit high speed FTL deign, working at maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (29.97 times or 96.7% better). Moreover, the same 18-bit high speed FTL adder outperforms other high performance adders, such as multilevel CSAs, in terms of both, energy efficiency (1.72 times) and propagation time delay (1.78 times). However, FTL is very sensitive to the device mismatch, and the variations in the capacitive loads in the the manufacturing process. We show how the the sensitivity of the FTL based design can be improved through very clever design techniques. This chapter also discusses the capabilities of the FTL logic in practical applications, and how to extend the use of this logic to larger word-length arithmetic circuits.||URI:||http://hdl.handle.net/10553/49646||ISBN:||9781617613258||Source:||CMOS Technology, p. 187-220|
|Appears in Collections:||Capítulo de libro|
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