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Title: A high-level design exploration of heterogeneous adders based on Mixed Integer Linear Programming
Authors: Montiel-Nelson, J. A. 
García-Montesdeoca, José C. 
Nooshabadi, Saeid
Sosa, J. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Delay
CMOS logic circuits
IP networks
Logic design
Issue Date: 2011
Journal: Midwest Symposium on Circuits and Systems 
Conference: 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 
Abstract: In this paper, we present a novel methodology based on Mixed Integer Linear Programming (MILP) for obtaining the complete design tradeoff curve of heterogeneous adders. For each optimal design point of the tradeoff curve, our approach determines both the number of subadders, the architecture of each subadder and the bit width of each subadder. In order to reduce the number of binary variables in the formulation of the MILP, we introduce a new modeling of non-convex curves. Comparisons using five different adder architectures implemented in a standard cells 65nm CMOS technology are shown. Experimental results reveal that the proposed design space exploration methodology is better, when compared with the best published work, up to 11.73 times and 2.16 times in average in terms of CPU time.
ISBN: 9781612848570
ISSN: 1548-3746
DOI: 10.1109/MWSCAS.2011.6026380
Source: Midwest Symposium on Circuits and Systems[ISSN 1548-3746] (6026380)
Appears in Collections:Actas de congresos
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