|Title:||Design of efficient SPARC cores for embedded systems||Authors:||Bautista, Tomas
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Embedded system
Electronic design automation and methodology
Microarchitecture, et al
|Issue Date:||1999||Journal:||Conference Proceedings of the EUROMICRO||Conference:||25th EUROMICRO Conference on Informatics: Theory and Practice for the New Millennium, EUROMICRO 1999||Abstract:||The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies' Epoch was used for the physical layout of the final circuits. These have been carried out in a 0.35 /spl mu/m, three-metal layer CMOS process. The description strategy and the design flow methodology allow us to obtain quantitative results that characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. This design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.||URI:||http://hdl.handle.net/10553/49299||ISBN:||0769503217||ISSN:||1089-6503||DOI:||10.1109/EURMIC.1999.794473||Source:||Conference Proceedings of the EUROMICRO[ISSN 1089-6503],v. 1 (794473), p. 236-239|
|Appears in Collections:||Actas de congresos|
Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.