Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49286
DC FieldValueLanguage
dc.contributor.authorJia, Z. J.en_US
dc.contributor.authorNúñez, A.en_US
dc.contributor.authorBautista, T.en_US
dc.contributor.authorPimentel, A. D.en_US
dc.contributor.otherBautista, Tomas-
dc.date.accessioned2018-11-24T05:55:10Z-
dc.date.available2018-11-24T05:55:10Z-
dc.date.issued2014en_US
dc.identifier.issn0141-9331en_US
dc.identifier.urihttp://hdl.handle.net/10553/49286-
dc.description.abstractIn this paper, we present a two-phase design space exploration (DSE) approach to address the problem of real-time application mapping on a flexible MPSoC platform. Our approach is composed of two independent phases - analytical estimation/pruning and system simulation - communicating via a well-defined interface. The strength of the resulting strategy is twofold. On one hand, it is capable of combining the benefits of analytical models and simulation tools (i.e., speed and accuracy). And on the other hand, separating pruning and evaluation phases facilitates the integration of different or additional pruning techniques as well as other existing simulation tools. Finally, we also present several proof-of-concept DSE experiments to illustrate distinct aspects and capabilities of our framework. These experimental results reveal that our approach, compared to other approaches based only on analytical estimation models or simulations guided by e.g. genetic algorithms, not only can explore a large design space and reach a valid solution in a time-efficient way, but also can provide solutions optimizing resource usage efficiency, system traffic and processor load balancing. (c) 2013 Elsevier B.V. All rights reserved.en_US
dc.languageengen_US
dc.publisher0141-9331-
dc.relation.ispartofMicroprocessors and Microsystemsen_US
dc.sourceMicroprocessors and Microsystems[ISSN 0141-9331],v. 38, p. 9-21en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherMP-SoC designen_US
dc.subject.otherSystem-level design space explorationen_US
dc.subject.otherComputer-aided designen_US
dc.subject.otherPerformance analysisen_US
dc.subject.otherMapping strategyen_US
dc.titleA two-phase design space exploration strategy for system-level real-time application mapping onto MPSoCen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.micpro.2013.10.005en_US
dc.identifier.scopus84888592071-
dc.identifier.isi000330751800002-
dcterms.isPartOfMicroprocessors And Microsystems-
dcterms.sourceMicroprocessors And Microsystems[ISSN 0141-9331],v. 38 (1), p. 9-21-
dc.contributor.authorscopusid55434973300-
dc.contributor.authorscopusid7103279517-
dc.contributor.authorscopusid6603190709-
dc.contributor.authorscopusid7003566212-
dc.description.lastpage21en_US
dc.description.firstpage9en_US
dc.relation.volume38en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:000330751800002-
dc.contributor.daisngid10393233-
dc.contributor.daisngid33795-
dc.contributor.daisngid2227678-
dc.contributor.daisngid506681-
dc.identifier.investigatorRIDA-9082-2011-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Jia, ZJ-
dc.contributor.wosstandardWOS:Nunez, A-
dc.contributor.wosstandardWOS:Bautista, T-
dc.contributor.wosstandardWOS:Pimentel, AD-
dc.date.coverdateEnero 2014en_US
dc.identifier.ulpgces
dc.description.sjr0,241
dc.description.jcr0,43
dc.description.sjrqQ2
dc.description.jcrqQ4
dc.description.scieSCIE
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.orcid0000-0002-5368-3680-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
crisitem.author.fullNameBautista Delgado, Tomás-
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