Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/49286
Title: A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC
Authors: Jia, Z. J.
Núñez, A. 
Bautista, T. 
Pimentel, A. D.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: MP-SoC design
System-level design space exploration
Computer-aided design
Performance analysis
Mapping strategy
Issue Date: 2014
Publisher: 0141-9331
Journal: Microprocessors and Microsystems 
Abstract: In this paper, we present a two-phase design space exploration (DSE) approach to address the problem of real-time application mapping on a flexible MPSoC platform. Our approach is composed of two independent phases - analytical estimation/pruning and system simulation - communicating via a well-defined interface. The strength of the resulting strategy is twofold. On one hand, it is capable of combining the benefits of analytical models and simulation tools (i.e., speed and accuracy). And on the other hand, separating pruning and evaluation phases facilitates the integration of different or additional pruning techniques as well as other existing simulation tools. Finally, we also present several proof-of-concept DSE experiments to illustrate distinct aspects and capabilities of our framework. These experimental results reveal that our approach, compared to other approaches based only on analytical estimation models or simulations guided by e.g. genetic algorithms, not only can explore a large design space and reach a valid solution in a time-efficient way, but also can provide solutions optimizing resource usage efficiency, system traffic and processor load balancing. (c) 2013 Elsevier B.V. All rights reserved.
URI: http://hdl.handle.net/10553/49286
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2013.10.005
Source: Microprocessors and Microsystems[ISSN 0141-9331],v. 38, p. 9-21
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