|Title:||Rapid-prototyping of high-performance RISC cores with VHDL||Authors:||Bautista, T.
Carballo, P. P.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Electronic design automation and methodology
Hardware design languages
Reduced instruction set computing, et al
|Issue Date:||1997||Journal:||Proceedings of the VHDL International Users Forum Fall Conference, VIUF||Conference:||VHDL-Internal-Users-Forum 1997 Fall Conference (VIUF 97)||Abstract:||In this paper we present some experiences we have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of high-performance embeddable cores.||URI:||http://hdl.handle.net/10553/48909||ISBN:||0-8186-8180-2||Source:||Proceedings of the VHDL International Users Forum Fall Conference, VIUF, p. 43-52|
|Appears in Collections:||Actas de congresos|
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