|Title:||Some experiences using system-on-chip buses||Authors:||Carballo, Pedro P.
Marrero Martín, Margarita
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||System-on-a-chip
Virtual colonoscopy, et al
|Issue Date:||2003||Journal:||Proceedings of SPIE - The International Society for Optical Engineering||Conference:||Conference on VLSI Circuits and Systems||Abstract:||Advances in fabrication and design technologies have contributed to integrate a complete system on a chip. A system-on-chip (SoC) is generally composed of a microprocessor core, on-clip memory and one or more specific coprocessors IPs. One of the major drawbacks of this approach is the differences in the interfaces that each virtual component (VC) of the SoC presents. The idea of a common bus infrastructure allows us to smooth the system integration and has been considered as a design solution for SoC architectures. This paper presents a review of different alternatives for SoC buses and summarizes some experiences of their use.||URI:||http://hdl.handle.net/10553/48907||ISBN:||0-8194-4977-6||ISSN:||0277-786X||DOI:||10.1117/12.501356||Source:||Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 329-340|
|Appears in Collections:||Actas de congresos|
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