Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/48828
Title: Network-on-chip emulation framework for multimedia SoC development
Authors: Singla, Garbí
Tobajas, Félix 
De Armas, Valentín D. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: System-On-Chip
Network-On-Chip
Fpga Emulation
Mpsoc
Issue Date: 2013
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Conference: 6th Conference on VLSI Circuits and Systems 
Abstract: Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is designed and implemented on a low-cost FPGA device. The objective of this work is the design and implementation of a prototyping platform with NoC topology, which provides a demonstrator for the implementation of multimedia applications. The emulation platform will allow evaluation, comparison, and verification of different aspects of a NoC design for SoCs intended for the execution of multimedia applications. The proposed emulation platform consists of different type of functional IP blocks (microprocessors, memory blocks, peripherals, additional blocks, etc.) interconnected through an interconnection infrastructure based on NoC. In order to provide a low-cost solution, the platform design is restricted to use a single FPGA, resulting in a low-scale SoC due to the limited resources available in the FPGA used. However, the proposed design may be scalable and replicate in large scale FPGA or multi-FPGA devices to increase emulation performance. In this work, a design flow, which integrates different commercial EDA tools, is presented, and integration process is discussed in detail due to problems experienced in this stage. The platform is fully implemented on a Xilinx Spartan-6 LX45T FPGA and special attention is given to verification and floorplanning stages. Finally, various multimedia applications with real-time requirements are executed on the NoC-based SoC platform. At this stage, the performance results are analyzed according to the type of application, as well as the number of processors required.
URI: http://hdl.handle.net/10553/48828
ISBN: 9780819495617
ISSN: 0277-786X
DOI: 10.1117/12.2017324
Source: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 8764 (876409)
Appears in Collections:Actas de congresos
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