An empirical model to estimate power consumption in GaAs DCFL/SDCFL circuits

Título:	An empirical model to estimate power consumption in GaAs DCFL/SDCFL circuits
Autores/as:	Hernández Ballester, Antonio Gómez, L. Nunez, A.
Clasificación UNESCO:	3307 Tecnología electrónica
Palabras clave:	VLSI Power Estimation CAD GaAs DCFL/SDCFL Optimization
Fecha de publicación:	1993
Publicación seriada:	Microprocessing and Microprogramming
Conferencia:	18Th Euromicro Conf - Software And Hardware : Specification And Design ( Euromicro 92 )
Resumen:	Power dissipation is a conflicting criterium for designing high performance VLSI GaAs circuits. This paper describes a power formulation to estimate the consumption in SDCFL/DCFL circuits. It uses polynomial expressions in order to fit the power values measured with HSPICE. Besides these expressions are suitable for incorporation into an optimization strategy. The agreement with measured results is excellent, with error less than 10% over the tested cases.
URI:	http://hdl.handle.net/10553/47618
ISSN:	0165-6074
DOI:	10.1016/0165-6074(93)90008-9
Fuente:	Microprocessing and Microprogramming [ISSN 0165-6074], v. 37 (1-5), p. 23-26
Colección:	Artículos

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