Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/46819
Title: MPEG-4 ASP SoC receiver with novel image enhancement techniques for DAB networks
Authors: Barreto, D.
Quintana, A.
García, L.
Callico, G. M. 
Núñez, A. 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Real-time systems
Digital Audio Broadcast
MPEG-4
Issue Date: 2007
Journal: Proceedings of SPIE - The International Society for Optical Engineering 
Abstract: This paper presents a system for real-time video reception in low-power mobile devices using Digital Audio Broadcast (DAB) technology for transmission. A demo receiver terminal is designed into a FPGA platform using the Advanced Simple Profile (ASP) MPEG-4 standard for video decoding. In order to keep the demanding DAB requirements, the bandwidth of the encoded sequence must be drastically reduced. In this sense, prior to the MPEG-4 coding stage, a pre-processing stage is performed. It is firstly composed by a segmentation phase according to motion and texture based on the Principal Component Analysis (PCA) of the input video sequence, and secondly by a down-sampling phase, which depends on the segmentation results. As a result of the segmentation task, a set of texture and motion maps are obtained. These motion and texture maps are also included into the bit-stream as user data side-information and are therefore known to the receiver. For all bit-rates, the whole encoder/decoder system proposed in this paper exhibits higher image visual quality than the alternative encoding/decoding method, assuming equal image sizes. A complete analysis of both techniques has also been performed to provide the optimum motion and texture maps for the global system, which has been finally validated for a variety of video sequences. Additionally, an optimal HW/SW partition for the MPEG-4 decoder has been studied and implemented over a Programmable Logic Device with an embedded ARM9 processor. Simulation results show that a throughput of 15 QCIF frames per second can be achieved with low area and low power implementation.
URI: http://hdl.handle.net/10553/46819
ISBN: 978-0-8194-6718-8
ISSN: 0277-786X
DOI: 10.1117/12.723740
Source: Vlsi Circuits And Systems Iii[ISSN 0277-786X],v. 6590
Appears in Collections:Actas de congresos
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