Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/46809
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Madronal, D. | en_US |
dc.contributor.author | Lazcano, R. | en_US |
dc.contributor.author | Fabelo, H. | en_US |
dc.contributor.author | Ortega, S. | en_US |
dc.contributor.author | Salvador, R. | en_US |
dc.contributor.author | Callico, G. M. | en_US |
dc.contributor.author | Juarez, E. | en_US |
dc.contributor.author | Sanz, C. | en_US |
dc.date.accessioned | 2018-11-23T08:26:08Z | - |
dc.date.available | 2018-11-23T08:26:08Z | - |
dc.date.issued | 2017 | en_US |
dc.identifier.isbn | 9781538635346 | en_US |
dc.identifier.issn | 2164-9766 | en_US |
dc.identifier.other | WoS | - |
dc.identifier.uri | http://hdl.handle.net/10553/46809 | - |
dc.description.abstract | In this paper, a Massively Parallel Processor Array platform is characterized in terms of energy consumption using a Support Vector Machine for hyperspectral image classification. This platform gathers 16 clusters composed of 16 cores each, i.e., 256 processors working in parallel. The objective of the work is to associate power dissipation and energy consumed by the platform with the different resources of the architecture. Experimenting with a hyperspectral SVM classifier, this study has been conducted using three strategies: i) modifying the number of processing elements, i.e., clusters and cores, ii) increasing system frequency, and iii) varying the number of active communication links during the analysis, i.e., I/Os and DMAs. As a result, a relationship between the energy consumption and the active platform resources has been exposed using two different parallelization strategies. Finally, the implementation that fully exploits the parallelization possibilities working at 500MHz has been proven to be also the most efficient one, as it reduces the energy consumption by 98% when compared to the sequential version running at 400MHz. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | 2017 Conference On Design And Architectures For Signal And Image Processing (Dasip) | en_US |
dc.source | Conference on Design and Architectures for Signal and Image Processing, DASIP[ISSN 2164-9766],v. 2017-September, p. 1-6 | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | Hyperspectral imaging | en_US |
dc.subject.other | Parallel processing | en_US |
dc.subject.other | Support vector machines | en_US |
dc.subject.other | Energy consumption | en_US |
dc.subject.other | Powe dissipation | en_US |
dc.subject.other | Power measurement | en_US |
dc.title | Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | 2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017 | en_US |
dc.identifier.doi | 10.1109/DASIP.2017.8122112 | en_US |
dc.identifier.scopus | 85041549514 | - |
dc.identifier.isi | 000426986300006 | - |
dc.contributor.authorscopusid | 57192829417 | - |
dc.contributor.authorscopusid | 57192839213 | - |
dc.contributor.authorscopusid | 56405568500 | - |
dc.contributor.authorscopusid | 57189334144 | - |
dc.contributor.authorscopusid | 23005852100 | - |
dc.contributor.authorscopusid | 56006321500 | - |
dc.contributor.authorscopusid | 36447485600 | - |
dc.contributor.authorscopusid | 7006751614 | - |
dc.description.lastpage | 6 | en_US |
dc.description.firstpage | 1 | en_US |
dc.relation.volume | 2017-September | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.contributor.daisngid | 3360488 | - |
dc.contributor.daisngid | 3634522 | - |
dc.contributor.daisngid | 2096372 | - |
dc.contributor.daisngid | 1812298 | - |
dc.contributor.daisngid | 1888017 | - |
dc.contributor.daisngid | 506422 | - |
dc.contributor.daisngid | 693458 | - |
dc.contributor.daisngid | 384271 | - |
dc.description.numberofpages | 6 | en_US |
dc.identifier.eisbn | 978-1-5386-3534-6 | - |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | WOS:Madronal, D | - |
dc.contributor.wosstandard | WOS:Lazcano, R | - |
dc.contributor.wosstandard | WOS:Fabelo, H | - |
dc.contributor.wosstandard | WOS:Ortega, S | - |
dc.contributor.wosstandard | WOS:Salvador, R | - |
dc.contributor.wosstandard | WOS:Callico, GM | - |
dc.contributor.wosstandard | WOS:Juarez, E | - |
dc.contributor.wosstandard | WOS:Sanz, C | - |
dc.date.coverdate | Noviembre 2017 | en_US |
dc.identifier.conferenceid | events121092 | - |
dc.identifier.ulpgc | Sí | es |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.event.eventsstartdate | 27-09-2017 | - |
crisitem.event.eventsenddate | 29-09-2017 | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-9794-490X | - |
crisitem.author.orcid | 0000-0002-7519-954X | - |
crisitem.author.orcid | 0000-0002-3784-5504 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | Fabelo Gómez, Himar Antonio | - |
crisitem.author.fullName | Ortega Sarmiento,Samuel | - |
crisitem.author.fullName | Marrero Callicó, Gustavo Iván | - |
Colección: | Actas de congresos |
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