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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45648
DC FieldValueLanguage
dc.contributor.authorSzydzik, Tomaszen_US
dc.contributor.authorNunez, Antonioen_US
dc.contributor.authorDe Paepe, Lodeen_US
dc.contributor.authorAlbani, Luigien_US
dc.date.accessioned2018-11-22T11:29:16Z-
dc.date.available2018-11-22T11:29:16Z-
dc.date.issued2013en_US
dc.identifier.isbn9789531841948en_US
dc.identifier.issn1845-5921en_US
dc.identifier.urihttp://hdl.handle.net/10553/45648-
dc.description.abstractHigh dynamic range displays based on dual panel LCD are a viable option for building a low-cost solution for providing high bit depth visualization systems. One of the factors limiting the usability of this type of displays are the computation requirements of the algorithm necessary for correct visualization using the two stacked panels. In this work we present the methodology and the results of mapping this algorithm on a CPU+GPU platform using the OpenCL 1.1 API. Visualization of a 2048×2048 image when executed on a CPU+GPU (AMD Radeon V7800) platform is performed up to 7.6 times faster then when only the CPU is used. The first results are promising and encourage the use of GPUs (or APUs) for acceleration of this kind of processing.en_US
dc.languageengen_US
dc.publisher1845-5921en_US
dc.relation.ispartofInternational Symposium on Image and Signal Processing and Analysis, ISPAen_US
dc.sourceInternational Symposium on Image and Signal Processing and Analysis, ISPA[ISSN 1845-5921] (06703789), p. 483-488en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherSignal processing algorithmsen_US
dc.subject.otherBiomedical imagingen_US
dc.subject.otherAlgorithm design and analysisen_US
dc.subject.otherGraphics processing unitsen_US
dc.subject.otherKernelen_US
dc.titleContributions to visualization algorithm enabling GPU-accelerated image displaying for dual panel high dynamic range LCD displayen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference8th International Symposium on Image and Signal Processing and Analysis (ISPA)
dc.relation.conference8th International Symposium on Image and Signal Processing and Analysis, ISPA 2013
dc.identifier.scopus84896380757-
dc.identifier.isi000349789200086
dc.contributor.authorscopusid39262669300-
dc.contributor.authorscopusid7103279517-
dc.contributor.authorscopusid8700677500-
dc.contributor.authorscopusid6602528213-
dc.description.lastpage488en_US
dc.identifier.issue06703789-
dc.description.firstpage483en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid5545091
dc.contributor.daisngid33795
dc.contributor.daisngid6715564
dc.contributor.daisngid1678784
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Szydzik, T
dc.contributor.wosstandardWOS:Nunez, A
dc.contributor.wosstandardWOS:de Paepe, L
dc.contributor.wosstandardWOS:Albani, L
dc.date.coverdateEnero 2013
dc.identifier.conferenceidevents120898
dc.identifier.ulpgcSíes
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.event.eventsstartdate04-09-2013-
crisitem.event.eventsstartdate04-09-2013-
crisitem.event.eventsenddate06-09-2013-
crisitem.event.eventsenddate06-09-2013-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameSzydzik, Tomasz-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
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