Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45647
DC FieldValueLanguage
dc.contributor.authorCarballo, Pedro P.en_US
dc.contributor.authorEspino, Omaren_US
dc.contributor.authorNeris, Roménen_US
dc.contributor.authorHernández-Fernández, Pedroen_US
dc.contributor.authorSzydzik, Tomasz M.en_US
dc.contributor.authorNúñez, Antonioen_US
dc.contributor.otherP. Carballo, Pedro-
dc.date.accessioned2018-11-22T11:28:50Z-
dc.date.available2018-11-22T11:28:50Z-
dc.date.issued2013en_US
dc.identifier.isbn9780819495617en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.urihttp://hdl.handle.net/10553/45647-
dc.description.abstractThis paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H. 264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high-level synthesis methodology to RTL microarchitecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies.The final implementation is chosen among the implementations that meet the timing constraints. The DF is capable to run at 100 MHz, and macroblocks are processed in 6,500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. The proposed architecture for the complete H. 264/SVC decoder is composed of an OMAP 3530 SOC (ARM Cortex-A8 GPP + DSP) and the FPGA Virtex-5 acting as a coprocessor for DF implementation. The DF is connected to the OMAP SOC using the GPMC interface.A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the frame generation and visualization in a TFT screen. The FPGA implements both the DF core and a GPMC slave core. Both cores are connected to the PowerPC440 embedded processor using LocalLink interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device.
dc.languageengen_US
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_US
dc.sourceProceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 8764 (876408)en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherField programmable gate arraysen_US
dc.subject.otherDecodingen_US
dc.subject.otherScalabilityen_US
dc.subject.otherDeblocking filteren_US
dc.titleImplementation of scalable video coding deblocking filter from high-level systemc descriptionen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceConference on VLSI Circuits and Systems VI
dc.relation.conference6th Conference on VLSI Circuits and Systems
dc.identifier.doi10.1117/12.2016885
dc.identifier.scopus84881152111-
dc.identifier.isi000323576000008-
dcterms.isPartOfVlsi Circuits And Systems Vi
dcterms.sourceVlsi Circuits And Systems Vi[ISSN 0277-786X],v. 8764
dc.contributor.authorscopusid6602499289-
dc.contributor.authorscopusid57212880340
dc.contributor.authorscopusid55813409200-
dc.contributor.authorscopusid55812965200-
dc.contributor.authorscopusid55813327100-
dc.contributor.authorscopusid39262669300-
dc.contributor.authorscopusid7103279517-
dc.identifier.issue876408-
dc.relation.volume8764en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Actas de congresosen_US
dc.identifier.wosWOS:000323576000008-
dc.contributor.daisngid3056889-
dc.contributor.daisngid4389544-
dc.contributor.daisngid12565557-
dc.contributor.daisngid8919282-
dc.contributor.daisngid5545091-
dc.contributor.daisngid33795-
dc.identifier.investigatorRIDF-6600-2014-
dc.utils.revisionen_US
dc.contributor.wosstandardWOS:Carballo, PP
dc.contributor.wosstandardWOS:Espino, O
dc.contributor.wosstandardWOS:Neris, R
dc.contributor.wosstandardWOS:Hernandez-Fernandez, P
dc.contributor.wosstandardWOS:Szydzik, TM
dc.contributor.wosstandardWOS:Nunez, A
dc.date.coverdateAgosto 2013
dc.identifier.conferenceidevents120838
dc.identifier.ulpgces
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptIUMA Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0001-7912-8768-
crisitem.author.orcid0000-0003-3848-2116-
crisitem.author.orcid0000-0003-1295-1594-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNamePérez Carballo, Pedro Francisco-
crisitem.author.fullNameHernández Fernández, Pedro-
crisitem.author.fullNameSzydzik, Tomasz-
crisitem.author.fullNameNúñez Ordóñez, Antonio-
crisitem.event.eventsstartdate24-04-2013-
crisitem.event.eventsstartdate24-04-2013-
crisitem.event.eventsenddate26-04-2013-
crisitem.event.eventsenddate26-04-2013-
Appears in Collections:Actas de congresos
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