Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/45500
Campo DC Valoridioma
dc.contributor.authorMiatliuk, Kanstantsinen_US
dc.contributor.authorDíaz-Cabrera, Moisesen_US
dc.date.accessioned2018-11-22T10:19:55Z-
dc.date.available2018-11-22T10:19:55Z-
dc.date.issued2013en_US
dc.identifier.isbn9783642538612en_US
dc.identifier.issn0302-9743en_US
dc.identifier.urihttp://hdl.handle.net/10553/45500-
dc.description.abstractThe paper shows the possibility of Hierarchical Systems (HS) technology use in the tasks of Printed Circuit Boards (PCB) geometric design and interconnections (conductive pathways) quality testing. It gives formal description of the PCB construction and both the design and testing processes. Presented HS technology allows easy correction of interconnections topology of PCB, the mechanism of information aggregation permits reduction of computer memory, availability of coordinator allows performing decision making tasks on its layers. Possibility of HS technology realization using standard computer program and technical means is shown in the work as well.
dc.languagespaen_US
dc.publisher0302-9743en_US
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.sourceLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)[ISSN 0302-9743],v. 8112 LNCS, p. 521-526en_US
dc.titleApplication of hierarchical systems technology in design and testing of circuit boardsen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conference14th International Conference on Computer Aided Systems Theory (EUROCAST)en_US
dc.identifier.doi10.1007/978-3-642-53862-9_66en_US
dc.identifier.scopus84892610636-
dc.identifier.isi000378303900066-
dc.contributor.authorscopusid56006796300-
dc.contributor.authorscopusid36760594500-
dc.description.lastpage526en_US
dc.description.firstpage521en_US
dc.relation.volume8112 LNCSen_US
dc.type2Actas de congresosen_US
dc.contributor.daisngid2041569-
dc.contributor.daisngid29956019-
dc.contributor.wosstandardWOS:Miatliuk, K-
dc.contributor.wosstandardWOS:Diaz-Cabrera, M-
dc.date.coverdateDiciembre 2013en_US
dc.identifier.conferenceidevents121494-
dc.identifier.conferenceidevents121494-
dc.identifier.ulpgces
dc.description.sjr0,329
dc.description.sjrqQ3
item.grantfulltextnone-
item.fulltextSin texto completo-
crisitem.author.deptGIR IDeTIC: División de Procesado Digital de Señales-
crisitem.author.deptIU para el Desarrollo Tecnológico y la Innovación-
crisitem.author.deptDepartamento de Física-
crisitem.author.orcid0000-0003-3878-3867-
crisitem.author.parentorgIU para el Desarrollo Tecnológico y la Innovación-
crisitem.author.fullNameDíaz Cabrera, Moisés-
crisitem.event.eventsstartdate10-02-2013-
crisitem.event.eventsenddate15-02-2013-
Colección:Actas de congresos
Vista resumida

Citas SCOPUSTM   

1
actualizado el 24-mar-2024

Citas de WEB OF SCIENCETM
Citations

1
actualizado el 25-feb-2024

Visitas

61
actualizado el 24-ene-2024

Google ScholarTM

Verifica

Altmetric


Comparte



Exporta metadatos



Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.