Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/45093
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | López Feliciano, José Francisco | en_US |
| dc.contributor.author | Sarmiento, R. | en_US |
| dc.contributor.author | Nunez, A. | en_US |
| dc.contributor.author | Eshraghian, K. | en_US |
| dc.contributor.other | Lopez, Jose | - |
| dc.contributor.other | Sarmiento, Roberto | - |
| dc.date.accessioned | 2018-11-22T07:12:52Z | - |
| dc.date.available | 2018-11-22T07:12:52Z | - |
| dc.date.issued | 1996 | en_US |
| dc.identifier.isbn | 0-7803-3302-0 | en_US |
| dc.identifier.issn | 1063-0988 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10553/45093 | - |
| dc.description.abstract | In this paper Pseudo Dynamic Latched Logic (PDLL) is introduced. This class of logic takes benefits of both static and dynamic structures, by using a permanently refreshing circuitry which allows functionality even at low frequencies and high temperatures. Moreover, because of its dynamic structure, complex gates are possible with a subsequent delay-area-power reduction. PDLL performance is demonstrated by implementing a 4-bit carry lookahead adder fully operative in a range of 6 to 100/spl deg/C. The adder operates at 0.8 GHz with an associated power dissipation of only 5.2 mW. | en_US |
| dc.language | eng | en_US |
| dc.publisher | 1063-0988 | en_US |
| dc.relation.ispartof | Proceedings of the Annual IEEE International ASIC Conference and Exhibit | en_US |
| dc.source | Proceedings of the Annual IEEE International ASIC Conference and Exhibit[ISSN 1063-0988], p. 51-55 | en_US |
| dc.subject | 3307 Tecnología electrónica | en_US |
| dc.subject.other | Gallium arsenide | en_US |
| dc.subject.other | Power dissipation | en_US |
| dc.subject.other | CMOS technology | en_US |
| dc.subject.other | Leakage current | en_US |
| dc.subject.other | High performance computing | en_US |
| dc.subject.other | Frequency | en_US |
| dc.subject.other | Logic devices | en_US |
| dc.title | High performance GaAs pseudo dynamic class of logic | en_US |
| dc.type | info:eu-repo/semantics/conferenceObject | en_US |
| dc.type | ConferenceObject | en_US |
| dc.relation.conference | 9th Annual IEEE International ASIC Conference and Exhibit | en_US |
| dc.identifier.scopus | 0029746871 | - |
| dc.identifier.isi | A1996BG49N00011 | - |
| dcterms.isPartOf | Ninth Annual Ieee International Asic Conference And Exhibit, Proceedings | |
| dcterms.source | Ninth Annual Ieee International Asic Conference And Exhibit, Proceedings, p. 51-55 | |
| dc.contributor.authorscopusid | 7404444793 | - |
| dc.contributor.authorscopusid | 35609452100 | - |
| dc.contributor.authorscopusid | 7103279517 | - |
| dc.contributor.authorscopusid | 7007041524 | - |
| dc.description.lastpage | 55 | en_US |
| dc.description.firstpage | 51 | en_US |
| dc.investigacion | Ingeniería y Arquitectura | en_US |
| dc.type2 | Actas de congresos | en_US |
| dc.identifier.wos | WOS:A1996BG49N00011 | - |
| dc.contributor.daisngid | 846472 | - |
| dc.contributor.daisngid | 116294 | - |
| dc.contributor.daisngid | 4824549 | - |
| dc.contributor.daisngid | 33795 | - |
| dc.contributor.daisngid | 228382 | - |
| dc.identifier.investigatorRID | L-6046-2014 | - |
| dc.identifier.investigatorRID | L-6017-2014 | - |
| dc.utils.revision | Sí | en_US |
| dc.contributor.wosstandard | WOS:Lopez, JF | - |
| dc.contributor.wosstandard | WOS:Sarmiento, R | - |
| dc.contributor.wosstandard | WOS:Nunez, A | - |
| dc.contributor.wosstandard | WOS:Eshraghian, K | - |
| dc.date.coverdate | Enero 1996 | en_US |
| dc.identifier.conferenceid | events121221 | - |
| dc.identifier.ulpgc | Sí | es |
| dc.contributor.buulpgc | BU-ING | en_US |
| item.grantfulltext | none | - |
| item.fulltext | Sin texto completo | - |
| crisitem.event.eventsstartdate | 23-09-1996 | - |
| crisitem.event.eventsenddate | 27-09-1996 | - |
| crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.orcid | 0000-0002-6304-2801 | - |
| crisitem.author.orcid | 0000-0002-4843-0507 | - |
| crisitem.author.orcid | 0000-0003-1295-1594 | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.fullName | López Feliciano, José Francisco | - |
| crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
| crisitem.author.fullName | Núñez Ordóñez, Antonio | - |
| Appears in Collections: | Actas de congresos | |
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