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Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45089
DC FieldValueLanguage
dc.contributor.authorEshraghian, K.en_US
dc.contributor.authorLachowicz, S. W.en_US
dc.contributor.authorLópez Feliciano, José Franciscoen_US
dc.contributor.authorSarmiento, R.en_US
dc.contributor.otherSarmiento, Roberto-
dc.contributor.otherLopez, Jose-
dc.date.accessioned2018-11-22T07:11:08Z-
dc.date.available2018-11-22T07:11:08Z-
dc.date.issued1997en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://hdl.handle.net/10553/45089-
dc.description.abstractA Muller-C element is a fundamental building block of a handshake path in self-timed digital circuits. It is a basic event driven logic (EDL) gate, implementing the AND function for events. The authors present a new, improved design of the Muller-C element using GaAs MESFET technology. A static Muller-C gate is implemented that incorporates modifications of newly introduced, GaAs pseudodynamic latched logic family (PDLL) primitives. The circuit is characterised by very high speed and low power dissipation.en_US
dc.languageengen_US
dc.publisher0013-5194
dc.relation.ispartofElectronics lettersen_US
dc.sourceElectronics Letters[ISSN 0013-5194],v. 33, p. 757-759en_US
dc.subject3307 Tecnología electrónicaen_US
dc.subject.otherGallium arsenideen_US
dc.subject.otherSelf-timed digital circuitsen_US
dc.subject.otherPower dissipationen_US
dc.titleEfficient design of gallium arsenide Muller-C elementen_US
dc.typeinfo:eu-repo/semantics/Articleen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el:19970503en_US
dc.identifier.scopus0031121977-
dc.identifier.isiA1997WX45900023-
dcterms.isPartOfElectronics Letters
dcterms.sourceElectronics Letters[ISSN 0013-5194],v. 33 (9), p. 757-759
dc.contributor.authorscopusid7007041524-
dc.contributor.authorscopusid6602090999-
dc.contributor.authorscopusid7404444793-
dc.contributor.authorscopusid35609452100-
dc.description.lastpage759en_US
dc.description.firstpage757en_US
dc.relation.volume33en_US
dc.investigacionIngeniería y Arquitecturaen_US
dc.type2Artículoen_US
dc.identifier.wosWOS:A1997WX45900023-
dc.contributor.daisngid30404478-
dc.contributor.daisngid228382-
dc.contributor.daisngid1175732-
dc.contributor.daisngid846472-
dc.contributor.daisngid116294-
dc.identifier.investigatorRIDL-6017-2014-
dc.identifier.investigatorRIDL-6046-2014-
dc.utils.revisionSíen_US
dc.contributor.wosstandardWOS:Eshraghian, K-
dc.contributor.wosstandardWOS:Lachowicz, SW-
dc.contributor.wosstandardWOS:Lopez, JF-
dc.contributor.wosstandardWOS:Sarmiento, R-
dc.date.coverdateAbril 1997en_US
dc.identifier.ulpgcSíen_US
dc.contributor.buulpgcBU-TELen_US
dc.description.jcr1,005
dc.description.jcrqQ1
dc.description.scieSCIE
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-6304-2801-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameLópez Feliciano, José Francisco-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
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