Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45080
Title: High speed GaAs subsystem design using feed through logic
Authors: Montiel Nelson, Juan Antonio 
De Armas Sosa, Valentín 
Sarmiento Rodríguez, Roberto 
Núñez Ordóñez, Antonio 
Nooshabadi, S.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Gallium arsenide
Logic devices
Logic circuits
Delay
Feeds, et al
Issue Date: 1999
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Journal: Proceedings - Design, Automation, and Test in Europe Conference and Exhibition 
Conference: Design, Automation and Test in Europe Conference and Exhibition (DATE 1999) 
Abstract: In this paper design of fast arithmetic circuits using a GaAs based feed through logic (FTL) family is presented. A modified version of FTL termed differential FTL (DFTL) is introduced and basic aspects of design methodologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of device count, chip area, delay clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators.
URI: http://hdl.handle.net/10553/45080
ISBN: 0-7695-0078-1
ISSN: 1530-1591
DOI: 10.1109/DATE.1999.761174
Source: Proceedings - Design, Automation, and Test in Europe Conference and Exhibition [ISSN 1530-1591] (761174), p. 509-513
Appears in Collections:Actas de congresos
Show full item record

SCOPUSTM   
Citations

2
checked on May 16, 2021

Page view(s)

75
checked on May 16, 2021

Google ScholarTM

Check

Altmetric


Share



Export metadata



Items in accedaCRIS are protected by copyright, with all rights reserved, unless otherwise indicated.