Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/45080
| Título: | High speed GaAs subsystem design using feed through logic | Autores/as: | Montiel Nelson, Juan Antonio De Armas Sosa, Valentín Sarmiento Rodríguez, Roberto Núñez Ordóñez, Antonio Nooshabadi, S. |
Clasificación UNESCO: | 3307 Tecnología electrónica | Palabras clave: | Gallium arsenide Logic devices Logic circuits Delay Feeds, et al. |
Fecha de publicación: | 1999 | Editor/a: | Institute of Electrical and Electronics Engineers (IEEE) | Publicación seriada: | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition | Conferencia: | Design, Automation and Test in Europe Conference and Exhibition (DATE 1999) | Resumen: | In this paper design of fast arithmetic circuits using a GaAs based feed through logic (FTL) family is presented. A modified version of FTL termed differential FTL (DFTL) is introduced and basic aspects of design methodologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of device count, chip area, delay clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators. | URI: | http://hdl.handle.net/10553/45080 | ISBN: | 0-7695-0078-1 | ISSN: | 1530-1591 | DOI: | 10.1109/DATE.1999.761174 | Fuente: | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition [ISSN 1530-1591] (761174), p. 509-513 |
| Colección: | Actas de congresos |
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