Morphological processor for image applications and its implementation using GaAs technology

Abstract

Mathematical Morphology appears as a theory that can solve some drawbacks of the classical lineal image processing. Linear filters generate a spatial distortion from initial image, what give as result that specific algorithms are usually needed for each process with a complexity that can not be implemented in VLSI systems for Real Time Image Processing. Mathematical Morphology is an alternative method to overcome the inherent drawbacks of the linear processing based on the comparison of an initial image with some well known geometric figures. In this paper we present the implementation of a specific processor that computes Mathematical Morphology (MM) basic operations. Using a clock frequency of 250 MHz this processor is able to handle real time 512×512 pixels video images. Mathematical Morphology allows the non-linear processing of images and it is based on Dilation and Erosion operations using a geometric figure called Structural Element (SE). More complex image processing can be performed using these basic operations. In this implementation the structural element of 3×3 pixels was chosen. 0.6 μm HGaAsIV standard cells technology, from Vitesse Semiconductor Corporation, has been used achieving a logic level gate description with the possibility of migration to another technologies.