A compact layout technique to minimize high frequency switching effects in high speed circuits

Abstract

A full-custom layout style and its cell model are presented. The power supply and ground rail distribution is not only of very low self-inductance, but it is also independent of cell dimensions. Cell layouts following the proposed model greatly improves switching current effects at high frequency. The underlying cell architecture is regular and suitable for design automation without sacrificing any advantages of the full-custom design. Comparisons demonstrate that the layout of combinational circuits in the high speed cell model are compact and minimize the routing area. A cell compiler is used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. It is shown that the cell and macrocell compiler can generate complex and compact layouts. The technique is demonstrated for GaAs processes up to 4 GHz, but it can be directly applied to deep submicron CMOS processes as well.