|Title:||A compact layout technique to minimize high frequency switching effects in high speed circuits||Authors:||Montiel-Nelson, Juan A.
De Armas Sosa, Valentín
Sarmiento Rodríguez, Roberto
Núñez Ordóñez, Antonio
|UNESCO Clasification:||3307 Tecnología electrónica
220302 Elementos de circuitos
CMOS logic circuits
Power supplies, et al
|Issue Date:||2001||Publisher:||Institute of Electrical and Electronics Engineers (IEEE)||Journal:||Materials Research Society Symposium - Proceedings||Conference:||2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001||Abstract:||A full-custom layout style and its cell model are presented. The power supply and ground rail distribution is not only of very low self-inductance, but it is also independent of cell dimensions. Cell layouts following the proposed model greatly improves switching current effects at high frequency. The underlying cell architecture is regular and suitable for design automation without sacrificing any advantages of the full-custom design. Comparisons demonstrate that the layout of combinational circuits in the high speed cell model are compact and minimize the routing area. A cell compiler is used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. It is shown that the cell and macrocell compiler can generate complex and compact layouts. The technique is demonstrated for GaAs processes up to 4 GHz, but it can be directly applied to deep submicron CMOS processes as well.||URI:||http://hdl.handle.net/10553/45075||ISBN:||0-7803-6685-9||ISSN:||0272-9172||DOI:||10.1109/ISCAS.2001.922179||Source:||ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings,v. 4 (922179), p. 96-99|
|Appears in Collections:||Actas de congresos|
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