Please use this identifier to cite or link to this item:
http://hdl.handle.net/10553/45072
| Title: | ATM over SDH: Design of a STM-16c transceiver using GaAs technology | Authors: | Tubío, O. Esper-Chaín, R. González, F. Tobajas, F. De Armas Sosa, Valentín Montiel Nelson, Juan Antonio Sarmiento, R. |
UNESCO Clasification: | 3307 Tecnología electrónica | Keywords: | Direct Coupled FET Logic Synchronous Digital Hierarchy Asynchronous Transfer Mode STM-16c OC-48c |
Issue Date: | 2002 | Publisher: | 0026-2692 | Journal: | Microelectronics | Abstract: | This article describes an ATM transceiver implementation with add/drop function over Synchronous Digital Hierarchy (SDH) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using Direct Coupled FET Logic (DCFL) standard cells and obtaining, in this way, a logic gate level description which could be easily exportable to any technology. | URI: | http://hdl.handle.net/10553/45072 | ISSN: | 0026-2692 | DOI: | 10.1016/S0026-2692(02)00115-5 | Source: | Microelectronics Journal[ISSN 0026-2692],v. 33, p. 1097-1105 |
| Appears in Collections: | Artículos |
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