Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/45061
Título: A macromodel for exact computation of propagation delay time in GaAs and CMOS technologies
Autores/as: García, José C.
Montiel-Nelson, Juan A. 
Sosa, J. 
Navarro, Héctor
Sarmiento, R. 
Clasificación UNESCO: 3307 Tecnología electrónica
Palabras clave: Transistors
Cell library
Cytology
Fecha de publicación: 2003
Publicación seriada: Proceedings of SPIE - The International Society for Optical Engineering 
Conferencia: Conference on VLSI Circuits and Systems 
VLSI Circuits and Systems 
Resumen: A new transient macromodel for the cells used in Direct Coupled FET Logic (DCFL) GaAs and CMOS digital design is introduced in this paper. The numerical solution determines accurate propagation delay times. The macromodel is based on the differential equation for the output voltage in terms of currents and capacitances. Good agreement is obtained between the HSPICE simulation and the computation of the propagation delays for DCFL GaAs and CMOS basic gates: INV, NOR, OR and NAND. There is no error between HSPICE and our computation of propagation delay time for the high to low (tphi) and low to high (tplh) transitions. In addition, computation time analysis is provided and numerical solutions is several orders of magnitude faster than HSPICE.
URI: http://hdl.handle.net/10553/45061
ISBN: 0-8194-4977-6
ISSN: 0277-786X
DOI: 10.1117/12.498586
Fuente: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 5117, p. 434-444
Colección:Actas de congresos
Vista completa

Visitas

115
actualizado el 24-ago-2024

Google ScholarTM

Verifica

Altmetric


Comparte



Exporta metadatos



Los elementos en ULPGC accedaCRIS están protegidos por derechos de autor con todos los derechos reservados, a menos que se indique lo contrario.