A macromodel for exact computation of propagation delay time in GaAs and CMOS technologies

Abstract

A new transient macromodel for the cells used in Direct Coupled FET Logic (DCFL) GaAs and CMOS digital design is introduced in this paper. The numerical solution determines accurate propagation delay times. The macromodel is based on the differential equation for the output voltage in terms of currents and capacitances. Good agreement is obtained between the HSPICE simulation and the computation of the propagation delays for DCFL GaAs and CMOS basic gates: INV, NOR, OR and NAND. There is no error between HSPICE and our computation of propagation delay time for the high to low (tphi) and low to high (tplh) transitions. In addition, computation time analysis is provided and numerical solutions is several orders of magnitude faster than HSPICE.