Please use this identifier to cite or link to this item:
https://accedacris.ulpgc.es/handle/10553/45056
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Esper-Chaín, R. | en_US |
| dc.contributor.author | Tobajas, F. | en_US |
| dc.contributor.author | Tubío, O. | en_US |
| dc.contributor.author | Arteaga, R. | en_US |
| dc.contributor.author | De Armas Sosa, Valentín | en_US |
| dc.contributor.author | Sarmiento, R. | en_US |
| dc.contributor.other | Sarmiento, Roberto | - |
| dc.date.accessioned | 2018-11-22T06:56:06Z | - |
| dc.date.available | 2018-11-22T06:56:06Z | - |
| dc.date.issued | 2005 | en_US |
| dc.identifier.issn | 1549-7747 | en_US |
| dc.identifier.uri | https://accedacris.ulpgc.es/handle/10553/45056 | - |
| dc.description.abstract | The maximum data rate in today's available multidrop backplanes is significantly limited due to signal integrity concerns. In this brief, a novel gigabit multidrop serial link configuration for high-speed digital systems based on newly developed asymmetrical broadband power splitters with matching trace impedance, is presented. The proposed power splitter features good impedance match at all ports without the insertion losses being inherent to common resistive power splitters. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate above 3.5 Gbps. | en_US |
| dc.language | eng | en_US |
| dc.publisher | 1549-7747 | |
| dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Express Briefs | en_US |
| dc.source | IEEE Transactions on Circuits and Systems II: Express Briefs[ISSN 1549-7747],v. 52, p. 5-9 | en_US |
| dc.subject | 3307 Tecnología electrónica | en_US |
| dc.subject.other | Digital communication | en_US |
| dc.subject.other | Packet switching | en_US |
| dc.subject.other | Signal integrity | en_US |
| dc.subject.other | Backplanes | en_US |
| dc.subject.other | Traansmission line | en_US |
| dc.title | A Gigabit Multidrop Serial Backplane for High-Speed Digital Systems Based on Asymmetrical Power Splitter | en_US |
| dc.type | info:eu-repo/semantics/Article | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | 10.1109/TCSII.2004.838661 | |
| dc.identifier.scopus | 12544251538 | - |
| dc.identifier.isi | 000226221000002 | - |
| dcterms.isPartOf | Ieee Transactions On Circuits And Systems Ii-Express Briefs | |
| dcterms.source | Ieee Transactions On Circuits And Systems Ii-Express Briefs[ISSN 1549-7747],v. 52 (1), p. 5-9 | |
| dc.contributor.authorscopusid | 6602504574 | - |
| dc.contributor.authorscopusid | 6602389338 | - |
| dc.contributor.authorscopusid | 6507146657 | - |
| dc.contributor.authorscopusid | 9639327600 | - |
| dc.contributor.authorscopusid | 6603181073 | - |
| dc.contributor.authorscopusid | 35609452100 | - |
| dc.description.lastpage | 9 | - |
| dc.description.firstpage | 5 | - |
| dc.relation.volume | 52 | - |
| dc.investigacion | Ingeniería y Arquitectura | en_US |
| dc.type2 | Artículo | en_US |
| dc.identifier.wos | WOS:000226221000002 | - |
| dc.contributor.daisngid | 1984698 | - |
| dc.contributor.daisngid | 800751 | - |
| dc.contributor.daisngid | 26063230 | |
| dc.contributor.daisngid | 4693922 | - |
| dc.contributor.daisngid | 16199790 | |
| dc.contributor.daisngid | 1809260 | - |
| dc.contributor.daisngid | 1262195 | - |
| dc.contributor.daisngid | 116294 | - |
| dc.identifier.investigatorRID | L-6017-2014 | - |
| dc.utils.revision | Sí | en_US |
| dc.contributor.wosstandard | WOS:Esper-Chain, R | |
| dc.contributor.wosstandard | WOS:Tobajas, F | |
| dc.contributor.wosstandard | WOS:Tubio, O | |
| dc.contributor.wosstandard | WOS:Arteaga, R | |
| dc.contributor.wosstandard | WOS:de Armas, V | |
| dc.contributor.wosstandard | WOS:Sarmiento, R | |
| dc.date.coverdate | Enero 2005 | |
| dc.identifier.ulpgc | Sí | es |
| dc.description.scie | SCIE | |
| item.fulltext | Sin texto completo | - |
| item.grantfulltext | none | - |
| crisitem.author.dept | GIR IUMA: Equipos y Sistemas de Comunicación | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Sistemas de Información y Comunicaciones | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
| crisitem.author.dept | IU de Microelectrónica Aplicada | - |
| crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
| crisitem.author.orcid | 0000-0002-8381-969X | - |
| crisitem.author.orcid | 0000-0002-3379-5052 | - |
| crisitem.author.orcid | 0000-0002-1017-8107 | - |
| crisitem.author.orcid | 0000-0002-4843-0507 | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
| crisitem.author.fullName | Esper-Chaín Falcón, Roberto | - |
| crisitem.author.fullName | Tobajas Guerrero, Félix Bernardo | - |
| crisitem.author.fullName | De Armas Sosa, Valentín | - |
| crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
| Appears in Collections: | Artículos | |
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