Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45053
Title: Low cost efficient architecture for H.264 motion estimation
Authors: López, Sebastián 
Tobajas, Félix 
Villar, Arturo
De Armas Sosa, Valentín 
López, José Fco 
Sarmiento, Roberto 
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Motion estimation
Automatic voltage control
Video coding
Video compression
Field programmable gate arrays
Power dissipation
Issue Date: 2005
Journal: Proceedings - IEEE International Symposium on Circuits and Systems 
Conference: IEEE International Symposium on Circuits and Systems (ISCAS) 
IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 
Abstract: A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the power dissipation. As result, the implementation of the architecture in a low cost commercial FPGA is outlined in this paper, showing characteristics such as a reduced area occupation and an appropriate range of operation frequencies that make the architecture suitable for portable multimedia devices.
URI: http://hdl.handle.net/10553/45053
ISBN: 0-7803-8834-8
ISSN: 0271-4310
DOI: 10.1109/ISCAS.2005.1464612
Source: Proceedings - IEEE International Symposium on Circuits and Systems[ISSN 0271-4310] (1464612), p. 412-415
Appears in Collections:Actas de congresos
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