|Title:||Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: The H.264/AVC deblocking filter||Authors:||Arbelo, C.
López Feliciano, José Francisco
Mignolet, J. Y.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Kernel
Automatic voltage control
|Issue Date:||2007||Journal:||Proceedings -Design, Automation and Test in Europe, DATE||Conference:||Design, Automation and Test in Europe Conference and Exhibition (DATE 07)||Abstract:||Deblocking filtering represents one of the most compute intensive tasks in an H.264/AVC standard video decoder due to its demanding memory accesses and irregular data flow. For these reasons, an efficient implementation poses big challenges, especially for programmable platforms. In this sense, the mapping of this decoder's functionality onto a C-programmable coarse-grained reconfigurable architecture named ADRES (architecture for dynamically reconfigurable embedded systems) is presented in this paper, including results from the evaluation of different topologies. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the filtering as well as an increase in the degree of instruction parallelism (ILP) when compared with an implementation on a very long instruction word (VLIW) dedicated processor. This demonstrates that high ILP is achievable on the ADRES even for irregular, data-dependent kernels.||URI:||http://hdl.handle.net/10553/45041||ISBN:||978-3-9810801-2-4||ISSN:||1530-1591||DOI:||10.1109/DATE.2007.364587||Source:||Proceedings -Design, Automation and Test in Europe, DATE[ISSN 1530-1591] (4211792), p. 177-182|
|Appears in Collections:||Actas de congresos|
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