Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/45040
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | López, S. | en_US |
dc.contributor.author | Kanstein, A. | en_US |
dc.contributor.author | López Feliciano, José Francisco | en_US |
dc.contributor.author | Berekovic, M. | en_US |
dc.contributor.author | Sarmiento, R. | en_US |
dc.contributor.author | Mignolet, J. Y. | en_US |
dc.contributor.other | Lopez, Sebastian | - |
dc.contributor.other | Lopez, Jose | - |
dc.date.accessioned | 2018-11-22T06:48:41Z | - |
dc.date.available | 2018-11-22T06:48:41Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-0-8194-6718-8 | en_US |
dc.identifier.issn | 0277-786X | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/45040 | - |
dc.description.abstract | The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long Instruction Word (VLIW) dedicated processor. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Proceedings of SPIE - The International Society for Optical Engineering | en_US |
dc.source | Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 6590 (65900A) | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | Image coding | en_US |
dc.subject.other | Video signal processing | en_US |
dc.subject.other | Motion estimation | en_US |
dc.title | Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | en_US |
dc.type | ConferenceObject | en_US |
dc.relation.conference | Conference on VLSI Circuits and Systems III | en_US |
dc.identifier.doi | 10.1117/12.722042 | en_US |
dc.identifier.scopus | 36248929891 | - |
dc.identifier.isi | 000250425000011 | - |
dcterms.isPartOf | Vlsi Circuits And Systems Iii | |
dcterms.source | Vlsi Circuits And Systems Iii[ISSN 0277-786X],v. 6590 | |
dc.contributor.authorscopusid | 57187722000 | - |
dc.contributor.authorscopusid | 23004960800 | - |
dc.contributor.authorscopusid | 7404444793 | - |
dc.contributor.authorscopusid | 7003626844 | - |
dc.contributor.authorscopusid | 35609452100 | - |
dc.contributor.authorscopusid | 6602335610 | - |
dc.identifier.issue | 65900A | - |
dc.relation.volume | 6590 | en_US |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.identifier.wos | WOS:000250425000011 | - |
dc.contributor.daisngid | 465777 | - |
dc.contributor.daisngid | 2587035 | - |
dc.contributor.daisngid | 846472 | - |
dc.contributor.daisngid | 491652 | - |
dc.contributor.daisngid | 116294 | - |
dc.contributor.daisngid | 1738263 | - |
dc.identifier.investigatorRID | L-8108-2014 | - |
dc.identifier.investigatorRID | L-6046-2014 | - |
dc.utils.revision | Sí | en_US |
dc.contributor.wosstandard | WOS:Lopez, S | - |
dc.contributor.wosstandard | WOS:Kanstein, A | - |
dc.contributor.wosstandard | WOS:Lopez, JF | - |
dc.contributor.wosstandard | WOS:Berekovic, M | - |
dc.contributor.wosstandard | WOS:Sarmiento, R | - |
dc.contributor.wosstandard | WOS:Mignolet, JY | - |
dc.date.coverdate | Noviembre 2007 | en_US |
dc.identifier.conferenceid | events120577 | - |
dc.identifier.ulpgc | Sí | es |
dc.contributor.buulpgc | BU-TEL | en_US |
item.fulltext | Sin texto completo | - |
item.grantfulltext | none | - |
crisitem.event.eventsstartdate | 02-05-2007 | - |
crisitem.event.eventsenddate | 04-05-2007 | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-2360-6721 | - |
crisitem.author.orcid | 0000-0002-6304-2801 | - |
crisitem.author.orcid | 0000-0002-4843-0507 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | López Suárez, Sebastián Miguel | - |
crisitem.author.fullName | López Feliciano, José Francisco | - |
crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
Colección: | Actas de congresos |
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