Implementation of a parametrizable router architecture for Networks-on-Chip (NoC) with Quality of Service (QoS) support

Abstract

Managing the complexity of designing Systems-on-Chip (SoC) containing billions of transistors requires decoupling computation from communication. Networks-on-Chip (NoC) have been proposed as a solution for managing this problem as they meet the reusability, scalability and parallelism requirements of these systems, while coping with power constraints and clock distribution. In this paper, the implementation of a router's architecture for NoC with both guaranteed and best-effort services support is described, and some synthesis results are presented. The proposed router architecture is parameterized on the number of virtual channels, the size of virtual channels, the number of virtual channels for guaranteed traffic, the relative priority of the guaranteed traffic, and the switching technique.