Identificador persistente para citar o vincular este elemento: http://hdl.handle.net/10553/45026
Título: Hardware implementation of a scheduler for high performance switches with Quality of Service support
Autores/as: Arteaga, R.
Tobajas, F. 
De Armas Sosa, Valentín 
Sarmiento, R. 
Clasificación UNESCO: 3307 Tecnología electrónica
Palabras clave: Field programmable gate arrays
Quality of Service (QoS)
Differentiated Services
Traffic Scheduling
Fecha de publicación: 2009
Publicación seriada: Proceedings of SPIE - The International Society for Optical Engineering 
Conferencia: VLSI Circuits and Systems IV 
Resumen: In this paper, the hardware implementation of a scheduler with QoS support is presented. The starting point is a Differentiated Service (DiffServ) network model. Each switch of this network classifies the packets in flows which are assigned to traffic classes depending of its requirements with an independent queue being available for each traffic class. Finally, the scheduler chooses the right queue in order to provide Quality of Service support. This scheduler considers the bandwidth distribution, introducing the time frame concept, and the packet delay, assigning a priority to each traffic class. The architecture of this algorithm is also presented in this paper describing their functionality and complexity. The architecture was described in Verilog HDL at RTL level. The complete system has been implemented in a Spartan-3 1000 FPGA device using ISE software from Xilinx, demonstrating it is a suitable design for high speed switches.
URI: http://hdl.handle.net/10553/45026
ISBN: 9780819476371
ISSN: 0277-786X
DOI: 10.1117/12.821522
Fuente: Proceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 7363 (73630B)
Colección:Actas de congresos
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