Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45024
Title: Processor customization for software implementation of the AES algorithm for wireless sensor networks
Authors: Suárez, Néstor
Callicó, Gustavo M. 
Sarmiento, Roberto 
Santana, Octavio
Abbo, Anteneh A.
UNESCO Clasification: 3307 Tecnología electrónica
Keywords: Advanced Encryption Standard (AES)
Wireless Sensor Networks (WSN)
code optimization
Issue Date: 2010
Publisher: 0302-9743
Journal: Lecture Notes in Computer Science 
Conference: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation 
19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009 
Abstract: The Advanced Encryption Algorithm (AES) has been the most widely used symmetric block cipher technique for providing security to applications adopting Wireless Sensor Networks (WSN). In this Paper, an efficient software implementation of the AES algorithm is described running on an application specific processor (ASIP) platform that has been developed for use in low-power wireless sensor node designs with low memory requirements. Experimental results show that up to 46.3% reduction in cycle count is achievable through extensive code optimization. Hardware customization are proposed to the ASIP template to further improve the code performance. The gains include cycle count reductions of 33.1% and 45.2% for encryption and decryption, respectively and 21.6% reduction in code memory.
URI: http://hdl.handle.net/10553/45024
ISBN: 978-3-642-11801-2
3642118011
ISSN: 0302-9743
DOI: 10.1007/978-3-642-11802-9_37
Source: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)[ISSN 0302-9743],v. 5953 LNCS, p. 326-335
Appears in Collections:Actas de congresos
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