|Title:||Exploration of hardware sharing for image encoders||Authors:||López, S.
Potter, P. G.
Cheung, P. Y.K.
|UNESCO Clasification:||3307 Tecnología electrónica||Keywords:||Video compression
Field programmable gate arrays
|Issue Date:||2010||Publisher:||1530-1591||Journal:||Proceedings -Design, Automation and Test in Europe, DATE||Conference:||Design, Automation and Test in Europe Conference and Exhibition (DATE)
Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
|Abstract:||Hardware sharing can be used to reduce the area and the power dissipation of a design. This is of particular interest in the field of image and video compression, where an encoder must deal with different design tradeoffs depending on the characteristics of the signal to be encoded and the constraints imposed by the users. This paper introduces a novel methodology for exploring the design space based on the amount of hardware sharing between different functional blocks, giving as a result a set of feasible solutions which are broad in terms of hardware cost and throughput capabilities. The proposed approach, inspired by the notion of a partition in set theory, has been applied to optimize and to evaluate the sharing alternatives of a group of image and video compression key computational kernels when mapped onto a Xilinx Virtex-5 FPGA.||URI:||http://hdl.handle.net/10553/45023||ISBN:||9783981080162||ISSN:||1530-1591||Source:||Proceedings -Design, Automation and Test in Europe, DATE[ISSN 1530-1591] (5457095), p. 1737-1742|
|Appears in Collections:||Actas de congresos|