Please use this identifier to cite or link to this item: http://hdl.handle.net/10553/45019
DC FieldValueLanguage
dc.contributor.authorMori, José A.en_US
dc.contributor.authorTobajas, Félixen_US
dc.contributor.authorSarmiento, Robertoen_US
dc.contributor.authorDe Armas, Valentinen_US
dc.date.accessioned2018-11-22T06:38:42Z-
dc.date.available2018-11-22T06:38:42Z-
dc.date.issued2011en_US
dc.identifier.isbn9780819486561en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.otherWoS-
dc.identifier.urihttp://hdl.handle.net/10553/45019-
dc.description.abstractThe growth of complexity and the requirements of on-chip technologies create the need for new architectures which generate solutions representing a compromise between complexity and power consumption, and Quality of Service (QoS) of the communications between the cores of a System-on-Chip (SoC). Network-on-Chip (NoC) arises as a solution to implement efficient interconnections in SoC. This new technology, due to its complexity, creates the need of specialized engineers who can design the intricate circuits that NoC requires. It is possible to reduce those specialization needs by using CAD tools. In this paper, one of this tools, called Arteris NoC Solution, is used for developing the proposed framework for NoC emulation. This software includes three different tools: NoCexplorer, for high-level simulation of an abstract model of the NoC, NoCcompiler, in which the NoC is defined and generated in HDL language, and NoCverifier, which performs simulations of the HDL code. Furthermore, a validation and characterization infrastructure was developed for the created NoC, which can be completely emulated in FPGA. This environment is composed by OCP traffic generators and receptors, which also can perform measurements over the created traffic, and a store and communication module, which is responsible for storing the results obtained from the emulation of the entire system in the FPGA, and send it to a PC. Once the data is stored in the PC, statistical analyses are performed, including a comparison of mean latency from high level simulations, RTL simulations and FPGA emulations. The analysis of the results is obtained from three scenarios with different NoC topologies for the same SoC design.-
dc.languageengen_US
dc.publisher0277-786Xen_US
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_US
dc.sourceProceedings of SPIE - The International Society for Optical Engineering[ISSN 0277-786X],v. 8067 (80670I)en_US
dc.subject3307 Tecnología electrónica-
dc.subject.otherFPGA emulation-
dc.subject.otherMPSoC-
dc.subject.otherNetwork on chip-
dc.subject.otherTraffic analysis-
dc.subject.otherTraffic generators-
dc.subject.otherQoS-
dc.titleNoC emulation framework based on Arteris NoC Solution for multiprocessor System-on-Chipen_US
dc.typeinfo:eu-repo/semantics/conferenceObjecten_US
dc.typeConferenceObjecten_US
dc.relation.conferenceConference on VLSI Circuits and Systems Ven_US
dc.identifier.doi10.1117/12.887474en_US
dc.identifier.scopus79958031312-
dc.identifier.isi000292763900017-
dc.contributor.authorscopusid41361609700-
dc.contributor.authorscopusid6602389338-
dc.contributor.authorscopusid6603181073-
dc.contributor.authorscopusid35609452100-
dc.identifier.issue80670I-
dc.relation.volume8067en_US
dc.investigacionIngeniería y Arquitectura-
dc.type2Actas de congresosen_US
dc.contributor.daisngid6086134-
dc.contributor.daisngid800751-
dc.contributor.daisngid13379932-
dc.contributor.daisngid116294-
dc.description.numberofpages11en_US
dc.utils.revision-
dc.contributor.wosstandardWOS:Mori, JA-
dc.contributor.wosstandardWOS:Tobajas, F-
dc.contributor.wosstandardWOS:de Armas, V-
dc.contributor.wosstandardWOS:Sarmiento, R-
dc.date.coverdateJunio 2011en_US
dc.identifier.conferenceidevents121406-
dc.identifier.ulpgc-
dc.contributor.buulpgcBU-TELen_US
item.fulltextSin texto completo-
item.grantfulltextnone-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.deptGIR IUMA: Sistemas de Información y Comunicaciones-
crisitem.author.deptIU de Microelectrónica Aplicada-
crisitem.author.deptDepartamento de Ingeniería Electrónica y Automática-
crisitem.author.orcid0000-0002-3379-5052-
crisitem.author.orcid0000-0002-4843-0507-
crisitem.author.orcid0000-0002-1017-8107-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.parentorgIU de Microelectrónica Aplicada-
crisitem.author.fullNameTobajas Guerrero, Félix Bernardo-
crisitem.author.fullNameSarmiento Rodríguez, Roberto-
crisitem.author.fullNameDe Armas Sosa, Valentín-
Appears in Collections:Actas de congresos
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