Identificador persistente para citar o vincular este elemento:
http://hdl.handle.net/10553/45016
Campo DC | Valor | idioma |
---|---|---|
dc.contributor.author | Horstrand, Pablo | en_US |
dc.contributor.author | Lopez, Sebastian | en_US |
dc.contributor.author | Callico, Gustavo M. | en_US |
dc.contributor.author | Lopez, Jose F. | en_US |
dc.contributor.author | Sarmiento, Roberto | en_US |
dc.date.accessioned | 2018-11-22T06:37:22Z | - |
dc.date.available | 2018-11-22T06:37:22Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.issn | 2158-6276 | en_US |
dc.identifier.uri | http://hdl.handle.net/10553/45016 | - |
dc.description.abstract | Hyperspectral images are nowadays used in multiple fields, such as medical diagnosis, assessment of food quality, or environmental monitoring, just to name some. Due to their inherent nature, a great number of these applications require the implementation of a real time hyperspectral image processing system. However, most of the research effort so far has been concentrated on the development of mathematical algorithms to process these images, rather than in the implementation of them into a piece of hardware able to face with real time requirements. In this paper, the architectural design and hardware implementation of two hyperspectral matching algorithms (spectral angle and cross correlation) onto a Virtex-5 FPGA device are presented. In this sense, the goal of this work is not only to reduce image processing times by mapping these algorithms onto a programmable hardware platform, but also to provide a comparison between them in different terms, such as area occupation and throughput, than the ones normally used in the hyperspectral literature. The results demonstrate the achievement of speed-up factors of almost 600 times when compared with pure software implementations, as well as the higher hardware efficiency of the spectral angle with respect to the cross correlation algorithm. In addition, the benefits of adopting a pipelined architectural approach for the implementation of both algorithms are also proved, leading to a reduction in the time required for processing one hyperspectral cube of more than one order of magnitude with respect to state-of-the-art FPGA implementations. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Workshop on Hyperspectral Image and Signal Processing, Evolution in Remote Sensing | en_US |
dc.source | Workshop on Hyperspectral Image and Signal Processing, Evolution in Remote Sensing[ISSN 2158-6276] (6080921) | en_US |
dc.subject | 3307 Tecnología electrónica | en_US |
dc.subject.other | Hyperspectral imaging | en_US |
dc.subject.other | Algorithm design and analysis | en_US |
dc.subject.other | Field programmable gate arrays | en_US |
dc.subject.other | Pipelines | en_US |
dc.subject.other | Computer architecture | en_US |
dc.title | Novel architectures for real-time matching in hyperspectral images | en_US |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dc.type | ConferenceObject | es |
dc.relation.conference | 3rd Workshop on Hyperspectral Image and Signal Processing: Evolution in Remote Sensing, WHISPERS 2011 | |
dc.identifier.doi | 10.1109/WHISPERS.2011.6080921 | |
dc.identifier.scopus | 84255167101 | - |
dc.contributor.authorscopusid | 54399861900 | - |
dc.contributor.authorscopusid | 57187722000 | - |
dc.contributor.authorscopusid | 56006321500 | - |
dc.contributor.authorscopusid | 7404444793 | - |
dc.contributor.authorscopusid | 35609452100 | - |
dc.identifier.issue | 6080921 | - |
dc.investigacion | Ingeniería y Arquitectura | en_US |
dc.type2 | Actas de congresos | en_US |
dc.utils.revision | Sí | en_US |
dc.date.coverdate | Diciembre 2011 | |
dc.identifier.conferenceid | events121420 | |
dc.identifier.ulpgc | Sí | es |
item.grantfulltext | none | - |
item.fulltext | Sin texto completo | - |
crisitem.event.eventsstartdate | 06-06-2011 | - |
crisitem.event.eventsenddate | 09-06-2011 | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.dept | GIR IUMA: Diseño de Sistemas Electrónicos Integrados para el procesamiento de datos | - |
crisitem.author.dept | IU de Microelectrónica Aplicada | - |
crisitem.author.dept | Departamento de Ingeniería Electrónica y Automática | - |
crisitem.author.orcid | 0000-0002-2360-6721 | - |
crisitem.author.orcid | 0000-0002-3784-5504 | - |
crisitem.author.orcid | 0000-0002-6304-2801 | - |
crisitem.author.orcid | 0000-0002-4843-0507 | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.parentorg | IU de Microelectrónica Aplicada | - |
crisitem.author.fullName | López Suárez, Sebastián Miguel | - |
crisitem.author.fullName | Marrero Callicó, Gustavo Iván | - |
crisitem.author.fullName | López Feliciano, José Francisco | - |
crisitem.author.fullName | Sarmiento Rodríguez, Roberto | - |
Colección: | Actas de congresos |
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